14 332 331 Computer Architecture and Assembly Language
14: 332: 331 Computer Architecture and Assembly Language Spring 06 Week 3 : Braches and Procedures [Adapted from Dave Patterson’s UCB CS 152 slides and Mary Jane Irwin’s PSU CSE 331 slides] 331 Week 3. 1 Spring 2006
Review: MIPS Organization q Arithmetic instructions – to/from the register file q Load/store word and byte instructions – from/to memory Memory Processor 1… 1100 Register File src 1 addr src 2 addr dst addr write data src 1 data 32 5 5 5 32 registers ($zero - $ra) 32 read/write addr 32 src 2 32 data read data 32 32 bits write data Fetch 32 ALU Exec 230 words Decode 32 32 32 4 0 byte address (big Endian) 331 Week 3. 2 5 1 6 2 32 bits 7 3 0… 1100 0… 1000 0… 0100 0… 0000 word address (binary) Spring 2006
Review: MIPS Instructions, so far Category Instr Op Code Example Meaning Arithmetic add 0 and 32 add $s 1, $s 2, $s 3 $s 1 = $s 2 + $s 3 (R format) subtract 0 and 34 sub $s 1, $s 2, $s 3 $s 1 = $s 2 - $s 3 Data load word 35 lw $s 1, 100($s 2) $s 1 = Memory($s 2+100) transfer store word 43 sw $s 1, 100($s 2) Memory($s 2+100) = $s 1 (I format) load byte 32 lb $s 1, 101($s 2) $s 1 = Memory($s 2+101) store byte 40 sb $s 1, 101($s 2) Memory($s 2+101) = $s 1 331 Week 3. 3 Spring 2006
Instructions for Making Decisions q Decision making instructions l l q alter the control flow i. e. , change the "next" instruction to be executed Why do we need decision making instructions? if (i==j) h = i + j; q MIPS conditional branch instructions: bne $s 0, $s 1, Label $s 0 $s 1 beq $s 0, $s 1, Label $s 0=$s 1 q #go to Label if Example: if (i==j) h = i + j; 331 Week 3. 4 Spring 2006
Assembling Branches q Instructions: bne $s 0, $s 1, Label $s 0 $s 1 beq $s 0, $s 1, Label $s 0=$s 1 6 bits q q 5 bits #go to Label if 5 bits op rs Machine Formats: rt 16 bit number 5 16 17 ? ? 4 16 17 ? ? I format How is the branch destination address specified? 331 Week 3. 5 Spring 2006
Specifying Branch Destinations q Could use a register (like lw and sw) and add to it the 16 -bit offset l - Instruction Address Register (PC = program counter) - its use is automatically implied by instruction - PC gets updated (PC+4) during the fetch cycle so that it holds the address of the next instruction bne $s 0, $s 1, Lab 1 add $s 3, $s 0, $s 1 PC Lab 1+PC: . . . which register? l limits the offset to -215 to +215 -1 from the (instruction after the) branch instruction, but - most branches are local anyway (principle of locality) l One optimization - Each instruction is 4 bytes long, and only word address is necessary (multiple of 4) - We can right shift the offset by 2 bits (divided by 4), and store the value - Essentially, it can cover -217 to +217 -1 offset 331 Week 3. 6 Spring 2006
Disassembling Branch Destinations q q The contents of the updated PC (PC+4) is added to the low order 16 bits of the branch instruction which is converted into a 32 bit value by l concatenating two low-order zeros to create an 18 bit number Why? ? l sign-extending those 18 bits The result is written into the PC if the branch condition is true prior to the next Fetch cycle from the low order 16 bits of the branch instruction 16 offset sign-extend 00 32 32 Add PC 32 331 Week 3. 7 32 4 32 Add 32 32 branch dst address ? Spring 2006
Assembling Branches Example q Assembly code bne $s 0, $s 1, Lab 1 add $s 3, $s 0, $s 1. . . Lab 1: q q Machine Format of bne: op rs rt 5 16 17 16 bit offset I format Remember l After the bne instruction is fetched, the PC is updated to address the add instruction (PC = PC + 4). l Two low-order zeros are concatenated to the offset number and that value sign-extended is added to the (updated) PC 331 Week 3. 8 Spring 2006
MIPS Organization Processor Memory Register File src 1 addr src 2 addr dst addr write data 5 5 5 1… 1100 src 1 data 32 32 registers ($zero - $ra) read/write addr src 2 32 data 32 32 32 bits br offset 32 PC Fetch PC = PC+4 Exec 32 Add 4 32 Add read data 32 32 32 write data 32 Decode 230 words 32 32 ALU 32 32 4 0 5 1 32 bits byte address (big Endian) 331 Week 3. 9 6 2 7 3 0… 1100 0… 1000 0… 0100 0… 0000 word address (binary) Spring 2006
Another Instruction for Changing Flow q MIPS also has an unconditional branch instruction or jump instruction: j q label Example: 331 Week 3. 10 #go to label if (i!=j) h=i+j; else h=i-j; Spring 2006
Assembling Jumps q q Instruction: j label Machine Format: op 2 q #go to label 26 -bit address J format ? ? How is the jump destination address specified? l As an absolute address formed by - concatenating the upper 4 bits of the current PC (now PC+4) to the 26 -bit address and - concatenating 00 as the 2 low-order bits 331 Week 3. 11 Spring 2006
Disassembling Jump Destinations q to create a 32 bit instruction address that is placed into the PC prior to the next Fetch cycle from the low order 26 bits of the jump instruction 26 00 32 32 PC 331 Week 3. 12 32 Spring 2006
Assembling Branches and Jumps q Assemble the MIPS machine code (in decimal is fine) for the following code sequence. Assume that the address of the beq instruction is 0 x 00400020 (hex address) Lab 1: Lab 2: 331 Week 3. 13 beq add j sub. . . $s 0, $s 1, Lab 1 $s 3, $s 0, $s 1 Lab 2 $s 3, $s 0, $s 1 Spring 2006
Compiling While Loops q Compile the assembly code for the C while loop where i is in $s 0, j is in $s 1, and k is in $s 2 while (i!=k) i=i+j; 331 Week 3. 14 Spring 2006
More Instructions for Making Decisions q We have beq, bne, but what about branch-if-lessthan? q New instruction: slt $t 0, $s 1 q # if $s 0 < $s 1 # then # $t 0 = 1 # else # $t 0 = 0 Machine format: op 0 331 Week 3. 15 rs rt 16 17 rd 8 funct 0 42 = 0 x 2 a Spring 2006 2
Other Branch Instructions q Can use slt, beq, bne, and the fixed value of 0 in register $zero to create all relative conditions l less than blt $s 1, $s 2, Label l less than or equal to ble $s 1, $s 2, Label l greater than bgt $s 1, $s 2, Label l great than or equal to bge $s 1, $s 2, Label q As pseudo instructions - recognized (and expanded) by the assembler q The assembler needs a reserved register ($at) l 331 Week 3. 16 there are policy of use conventions for registers Spring 2006
Another Instruction for Changing Flow q Most higher level languages have case or switch statements allowing the code to select one of many alternatives depending on a single value. q Instruction: jr q $t 1 #go to address in $t 1 Machine format: 331 Week 3. 17 op rs 0 9 funct 0 0 0 8 = 0 x 08 Spring 2006 2
Compiling a Case (Switch) Statement switch (k) { case 0: h=i+j; case 1: h=i+h; case 2: h=i-j; 331 Week 3. 18 break; /*k=0*/ break; /*k=1*/ break; /*k=2*/ Spring 2006
Instructions, so far Category Instr Op Code Example Meaning Arithmetic add 0 and 32 add $s 1, $s 2, $s 3 $s 1 = $s 2 + $s 3 (R format) subtract 0 and 34 sub $s 1, $s 2, $s 3 $s 1 = $s 2 - $s 3 Data load word 35 lw $s 1, 100($s 2) $s 1 = Memory($s 2+100) transfer store word 43 sw $s 1, 100($s 2) Memory($s 2+100) = $s 1 (I format) load byte 32 lb $s 1, 101($s 2) $s 1 = Memory($s 2+101) store byte 40 sb $s 1, 101($s 2) Memory($s 2+101) = $s 1 br on equal 4 beq $s 1, $s 2, L if ($s 1==$s 2) go to L br on not equal 5 bne $s 1, $s 2, L if ($s 1 !=$s 2) go to L set on less than 0 and 42 slt $s 1, $s 2, $s 3 if ($s 2<$s 3) $s 1=1 else $s 1=0 2 j 2500 go to 10000 jump register 0 and 8 jr $t 1 go to $t 1 jump and link 3 jal 2500 go to 10000; $ra=PC+4 Cond. Branch Uncond. Jump 331 Week 3. 19 jump Spring 2006
Logic Operations q Logic operations operate on individual bits of the operand. $t 2 = 0… 0 0000 1101 0000 $t 1 = 0… 0 0011 1100 0000 and $t 0, $t 1, $t 2 $t 0 = or $t 0, $t 1 $t 2 $t 0 = xor $t 0, $t 1, $t 2 $t 0 = nor $t 0, $t 1, $t 2 $t 0 = 331 Week 3. 20 Spring 2006
Logical Operations - Shifts q They move all the bits in a word to the left or right, filling the emptied bits with 0 s. l l q sll $t 2, $s 0, 4 srl $t 2, $s 0, 4 op rs 0 0 # shift left # shift right rt rd shamt 16 10 4 funct 0 Shifting left by i bits gives the same result as multiplying by 2 i. 331 Week 3. 21 Spring 2006
Procedures int leaf_example (int g, int h, int i, int j) { int f; f = (g+h) – (i+j); return f; } CALLEE void main(){ int f; f = leaf_example(1, 2, 3, 4); f ++; } 331 Week 3. 22 CALLER Spring 2006
Six Steps in Execution of a Procedure q Main routine (caller) places actual parameters in a place where the procedure (callee) can access them l $a 0 - $a 3: four argument registers q Caller transfers control to the callee q Callee acquires the storage resources needed q Callee performs the desired task q Callee places the result value in a place where the caller can access it l q $v 0 - $v 1: two value registers for result values Callee returns control to the caller l $ra: one return address register to return to the point of origin 331 Week 3. 23 Spring 2006
Instruction for Calling a Procedure q MIPS procedure call instruction (caller): jal q Procedure. Address #jump and link l Saves PC+4 in register $ra l Jump to address Procedure. Address Then (callee) can do procedure return with just jr $ra #return 331 Week 3. 24 Spring 2006
Compiling a Procedure int leaf_example (int g, int h, int i, int j) { int f; f = (g+h) – (i+j); return f; } 331 Week 3. 25 Spring 2006
MIPS Register Convention Name Register Number $zero $v 0 - $v 1 $a 0 - $a 3 $t 0 - $t 7 $s 0 - $s 7 $t 8 - $t 9 $gp $sp $fp $ra 0 2 -3 4 -7 8 -15 16 -23 24 -25 28 29 30 31 331 Week 3. 26 Usage the constant 0 returned values arguments temporaries saved values temporaries global pointer stack pointer frame pointer return address Should preserve on call? no no yes yes Spring 2006
Spilling Registers q Where does the callee save those registers? l it uses a stack – a last-in-first-out queue high addr q top of stack $sp One of the general registers, $sp, is used to address the stack (which “grows” from high address to low address) l add data onto the stack – push $sp = $sp – 4 data on stack at new $sp l low addr 331 Week 3. 27 remove data from the stack – pop data from stack at $sp = $sp + 4 Spring 2006
A Quick Aside q MIPS instruction for adding immediate values: addi $sp, 4 #$sp = $sp + 4 addi $sp, -4 #$sp = $sp - 4 q Another version of add in which one operand is a constant where the constant is kept inside the instruction itself q MIPS pseudoinstruction for multiplying: mul q $v 0, $a 0, $v 0 #$v 0 = $a 0 * $v 0 We will look at the machine representations for these instructions in the next lecture 331 Week 3. 28 Spring 2006
Nested Procedures q What happens to return addresses with nested procedures? int rt_1 (int i) { if (i == 0) return 0; else return rt_2(i-1); } caller: jal rt_1 next: . . . rt_1: to_2: 331 Week 3. 29 rt_2: bne add jr addi jal jr. . . $a 0, $zero, to_2 $v 0, $zero $ra $a 0, -1 rt_2 $ra Spring 2006
Nested Procedures Outcome caller: jal rt_1 next: . . . rt_1: to_2: rt_2: q bne add jr addi jal jr $a 0, $zero, to_2 $v 0, $zero $ra $a 0, -1 rt_2 $ra . . . On the call to rt_1, the return address (next in the caller routine) gets stored in $ra. What happens to the value in $ra (when i != 0) when rt_1 makes a call to rt_2? 331 Week 3. 30 Spring 2006
Saving the Return Address q Nested procedures (i passed in $a 0, return value in $v 0) high addr old TOS $sp low addr $ra q rt_1: bne $a 0, $zero, to_2 add jr to_2: addi sw sw addi jal bk_2: lw lw addi jr $v 0, $ra $sp, $ra, $a 0, rt_2 $a 0, $ra, $sp, $ra $zero, $zero $sp, -8 4($sp) 0($sp) $a 0, -1 0($sp) 4($sp) $sp, 8 Save the return address (and arguments) on the stack 331 Week 3. 31 Spring 2006
Compiling a Recursive Procedure q Calculating factorial: int fact (int n) { if (n < 1) return 1; else return (n * fact (n-1)); } q Recursive procedure (one that calls itself!) fact (0) = 1 fact (1) = 1 * 1 = 1 fact (2) = 2 * 1 = 2 fact (3) = 3 * 2 * 1 = 6 fact (4) = 4 * 3 * 2 * 1 = 24. . . q Assume n is passed in $a 0; result returned in $v 0 331 Week 3. 32 Spring 2006
Compiling a Recursive Procedure fact: addi sw sw slt beq addi jr $sp, $ra, $a 0, $t 0, $v 0, $sp, $ra L 1: $a 0, -1 #n >=1, so decrement n fact #call fact with (n-1) is where fact returns $a 0, 0($sp) #restore argument n $ra, 4($sp) #restore return address $sp, 8 #adjust stack pointer $v 0, $a 0, $v 0 #$v 0 = n * fact(n-1) $ra #return to caller addi jal #this bk_f: lw lw addi mul jr 331 Week 3. 33 $sp, -8 4($sp) 0($sp) $a 0, 1 $zero, L 1 $zero, 1 $sp, 8 #adjust stack pointer #save return address #save argument n #test for n < 1 #if n >=1, go to L 1 #else return 1 in $v 0 #adjust stack pointer #return to caller Spring 2006
Review: MIPS Instructions, so far Category Instr Op Code Example Meaning Arithmetic add 0 and 32 add $s 1, $s 2, $s 3 $s 1 = $s 2 + $s 3 (R format) subtract 0 and 34 sub $s 1, $s 2, $s 3 $s 1 = $s 2 - $s 3 Data load word 35 lw $s 1, 100($s 2) $s 1 = Memory($s 2+100) transfer store word 43 sw $s 1, 100($s 2) Memory($s 2+100) = $s 1 (I format) load byte 32 lb $s 1, 101($s 2) $s 1 = Memory($s 2+101) store byte 40 sb $s 1, 101($s 2) Memory($s 2+101) = $s 1 br on equal 4 beq $s 1, $s 2, L if ($s 1==$s 2) go to L br on not equal 5 bne $s 1, $s 2, L if ($s 1 !=$s 2) go to L set on less than 0 and 42 slt $s 1, $s 2, $s 3 if ($s 2<$s 3) $s 1=1 else $s 1=0 2 j 2500 go to 10000 jump register 0 and 8 jr $t 1 go to $t 1 jump and link 3 jal 2500 go to 10000; $ra=PC+4 Cond. Branch Uncond. Jump 331 Week 3. 34 jump Spring 2006
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