13 Sequential Circuit Timing o Objectives This section

13. Sequential Circuit Timing o Objectives This section covers several timing considerations encountered in the design of synchronous sequential circuits. It has the following objectives: n Define the following global timing parameters and show they can be derived from the basic timing parameters of flip-flops and gates. u. Maximum Clock Frequency u. Maximum allowable clock skew u. Global Setup and Hold Times n Discuss ways to control the loading of data into registers and show why gating the clock signal to do this is a poor design practice. Elec 326 13. 1 Sequential Circuit Timing

o Reading Assignment n Elec 326 Much of the information in this section is not in the Brown & Vranesic text. There is material on clock skew in section 10. 3. That section also discusses the effects of gating the clock. 13. 2 Sequential Circuit Timing

13. 1. Maximum Clock Frequency o The clock frequency for a synchronous sequential circuit is limited by the timing parameters of its flipflops and gates. This limit is called the maximum clock frequency for the circuit. The minimum clock period is the reciprocal of this frequency. o Relevant timing parameters n Gates: u. Propagation delays: min t. PLH, min t. PHL, max t. PLH, max t. PHL n Flip-Flops: u. Propagation delays: min t. PLH, min t. PHL, max t. PLH, max t. PHL u. Setup time: tsu u. Hold time: th Elec 326 13. 3 Sequential Circuit Timing

o Example TW ≥ max t. PFF + tsu n For the 7474, max t. PLH = 25 ns, max t. PHL = 40 ns, tsu = 20 ns TW ≥ max (max t. PLH + tsu, max t. PHL + tsu) TW ≥ max (25+20, 40+20) = 60 Elec 326 13. 4 Sequential Circuit Timing

o Example TW ≥ max t. PFF + max t. PINV + tsu Elec 326 13. 5 Sequential Circuit Timing

o Example TW ≥ max t. PFF + max t. PMUX + tsu Elec 326 13. 6 Sequential Circuit Timing

o Example Paths from Q 1 to Q 1: None Paths from Q 1 to Q 2: TW ≥ max t. PDFF +t. JKsu = 20 +10 = 30 ns TW ≥ max t. PDFF + max t. AND + t. JKsu = 20 + 12 + 10 = 42 ns Paths from Q 2 to Q 1: TW ≥ max t. PJKFF + t. OR + TDsu = 25 + 10 + 5 = 40 ns Paths from Q 2 to Q 2: TW ≥ max t. PJKFF + max t. AND + t. JKsu = 25 + 12 + 10 = 47 ns TW ≥ 47 ns Elec 326 13. 7 Sequential Circuit Timing

o Clock Skew n n If a clock edge does not arrive at different flip-flops at exactly the same time, then the clock is said to be skewed between these flip-flops. The difference between the times of arrival at the flip-flops is said to be the amount of clock skew. Clock skew is due to different delays on different paths from the clock generator to the various flip-flops. u. Different length wires (wires have delay) u. Gates (buffers) on the paths u. Flip-Flops that clock on different edges (need to invert clock for some flip-flops) u. Gating the clock to control loading of registers (a very bad idea) Elec 326 13. 8 Sequential Circuit Timing

o Example (Effect of clock skew on clock rate) n Clock C 2 skewed after C 1 TW ≥ max TPFF + max t. OR + tsu (if clock not skewed, i. e. , t. INV = 0) Elec 326 TW ≥ max TPFF + max t. OR + tsu - min t. INV (if clock skewed, i. e. , t. INV > 0) 13. 9 Sequential Circuit Timing

n Clock C 1 skewed after C 2 TW ≥ max TPFF + max t. OR + tsu (if clock not skewed, i. e. , t. INV = 0) TW ≥ max TPFF + max t. OR + tsu + max t. INV (if clock skewed, i. e. , t. INV > 0) Elec 326 13. 10 Sequential Circuit Timing

o Summary of maximum clock frequency calculations C 2 skewed after C 1: TW ≥ max TPFF + max t. NET + tsu - min t. INV C 2 skewed before C 1: TW ≥ max TPFF + max t. NET + tsu + max t. INV Elec 326 13. 11 Sequential Circuit Timing

o Example n For each of the following two connections find u. The minimum clock period u. The maximum and minimum delay from CLK to YOUT Elec 326 13. 12 Sequential Circuit Timing

n Circuit 1: n≥ 2 Minimum Clock Period: Tw ≥ max t. PFF + max t. QY + (n-2) max t. XY +max t. XD + tsu ≥ TW Tw ≥ max t. PFF + max t. QD + tsu Maximum Delay: TCY ≤ max t. PFF + max t. QY + (n-1) max t. XY Minimum Delay: TCY ≥ min t. PFF + min t. QY Elec 326 13. 13 Sequential Circuit Timing

n Circuit 2: n≥ 2 Minimum Clock Period: Tw ≥ max t. PFF + max t. XD + tsu Tw ≥ max t. PFF + max t. QD + tsu Maximum Delay: TCY ≤ max t. PFF + max (max t. XY, max t. QY) Minimum Delay: TCY ≥ min t. PFF + min (min t. XY, min t. QY) Elec 326 13. 14 Sequential Circuit Timing

13. 2. Maximum Allowable Clock Skew o How much skew between C 1 and C 2 can be tolerated in the following circuit? n Case 1: C 2 delayed after C 1 t. PFF > th + t. SK < min t. PFF - th Elec 326 13. 15 Sequential Circuit Timing

n Elec 326 Case 2: C 1 delayed from C 2 13. 16 Sequential Circuit Timing

o How does additional delay between the flip-flops affect the skew calculations? t. SK ≤ min t. PFF - th tsk ≤ min t. PFF + min t. MUX - th Elec 326 13. 17 Sequential Circuit Timing

o Summary of allowable clock skew calculations t. SK + th ≤ t. PFF + t. NET t. SK ≤ min t. PFF + min t. NET - th Elec 326 13. 18 Sequential Circuit Timing

o Example: What is the minimum clock period for the following circuit under the assumption that the clock C 2 is skewed after C 1 (i. e. , C 2 is delayed from C 1)? Elec 326 13. 19 Sequential Circuit Timing

n n n First calculate the maximum allowable clock skew. t. SK < min t. PFF + min t. N 1 - th Next calculate the minimum clock period due to the path from Q 1 to D 2. TW > max t. PFF + max t. N 1 + tsu - min t. SK Finally calculate the minimum clock period due to the path from Q 2 to D 1 TW > max t. PFF + max t. N 1 + tsu + max t. SK TW > max t. PFF + max t. N 2 + tsu + (min t. PFF + min t. N 1 - th) TW > max t. PFF + min t. PFF + max t. N 2 + min t. N 1 + tsu - th Elec 326 13. 20 Sequential Circuit Timing

13. 3. Global Setup Time, Hold Time and Propagation Delay o Global setup and hold times (data delayed) TSU = tsu + max t. NET Elec 326 13. 21 TH = th - min t. NET Sequential Circuit Timing

o Global setup & hold time (clock delayed) TSU = tsu - min t. C Elec 326 TH = th + max t. C 13. 22 Sequential Circuit Timing

o Global setup & hold time (data & clock delayed) TSU = tsu + max t. NET - min t. C Elec 326 13. 23 TH = th - min t. NET + max t. C Sequential Circuit Timing

o Global propagation delay TP = t. C + t. FF + t. NET Elec 326 13. 24 Sequential Circuit Timing

o Summary of global timing parameters TSU = tsu + max t. PN - min t. PC ≤ tsu + max t. PN TH = th + max t. PC - min t. PN ≤ th + max t. PC TP = t. PFF + t. PN + t. PC Elec 326 13. 25 Sequential Circuit Timing

o Example n Find TSU and TH for input signal LD relative to CLK. TSU = tsu +max t. NET - min t. C = tsu + max t. INV + max t. NAND - min t. INV TH = th - min t. NET + max t. C = th - min t. NAND + max TINV Elec 326 13. 26 Sequential Circuit Timing

13. 4. Register load control (gating the clock) o A very bad way to add a load control signal LD to a register that does not have one is shown below o The reason this is such a bad idea is illustrated by the following timing diagram. o The flip-flop sees two rising edges and will trigger twice. The only one we want is the second one. Elec 326 13. 27 Sequential Circuit Timing

o If LD was constrained to only change when the clock was low, then the only problem would be the clock skew. Elec 326 13. 28 Sequential Circuit Timing

o If gating the clock is the only way to control the loading of registers, then use the following approach: n Elec 326 There is still clock skew, but at least we only have one triggering edge. 13. 29 Sequential Circuit Timing

o The best way to add a LD control signal is as follows: Elec 326 13. 30 Sequential Circuit Timing

13. 5. Synchronous System Structure and Timing Elec 326 13. 31 Sequential Circuit Timing

13. 6. Tips & Tricks o Use timing diagrams to determine the timing properties of sequential circuits 13. 7. Pitfalls o Using typical timing values from the data sheet (use only max and/or min values) o Gating the clock Elec 326 13. 32 Sequential Circuit Timing

13. 8 Review o How the flip-flop and gate timing parameters affect the maximum possible clock frequency. n How clock skew affect maximum possible clock frequency. o How the delay of logic between flip-flops affects the maximum allowable clock skew. o How flip-flop setup and hold times are translated by the combinational logic delays to get global setup and hold times. o The detrimental effect of gating the clock signal. Elec 326 13. 33 Sequential Circuit Timing