11 2 3 HighLow Guessing Game 2 Clock

11. 2. 3 High-Low Guessing Game

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Clock. vhd LIBRARY IEEE; USE IEEE. STD_LOGIC_1164. ALL; ENTITY Clockdiv IS PORT ( Clk 25 Mhz: IN STD_LOGIC; Clk: OUT STD_LOGIC); END Clockdiv; ARCHITECTURE Behavior OF Clockdiv IS -CONSTANT max: INTEGER : = 1000; -- minimum to debounce switch CONSTANT max: INTEGER : = 5000000; -- good to see FSM states -CONSTANT max: INTEGER : = 10000000; -- 10000000; = 1 sec CONSTANT half: INTEGER : = max/2; SIGNAL count: INTEGER RANGE 0 TO max; BEGIN PROCESS BEGIN WAIT UNTIL Clk 25 Mhz'EVENT and Clk 25 Mhz = '1'; IF count < max THEN count <= count + 1; ELSE count <= 0; END IF; IF count < half THEN Clk <= '0'; ELSE Clk <= '1'; END IF; END PROCESS; END Behavior; 3

Bcd. vhd LIBRARY IEEE; USE IEEE. STD_LOGIC_1164. ALL; ENTITY BCD IS PORT ( in_bcd: IN std_logic_vector(3 DOWNTO 0); segs: OUT std_logic_vector(1 TO 7)); END BCD; ARCHITECTURE Behavioral OF BCD IS BEGIN PROCESS(in_bcd) BEGIN CASE in_bcd IS -- 0=on; 1=off WHEN "0000" => segs <= "0000001"; WHEN "0001" => Segs <= "1001111"; WHEN "0010" => Segs <= "0010010"; WHEN "0011" => Segs <= "0000110"; WHEN "0100" => Segs <= "1001100"; WHEN "0101" => Segs <= "0100100"; WHEN "0110" => Segs <= "0100000"; WHEN "0111" => Segs <= "0001111"; WHEN "1000" => Segs <= "0000000"; WHEN "1001" => Segs <= "0001100"; WHEN "1010" => Segs <= "0001000"; WHEN "1011" => Segs <= "1100000"; WHEN "1100" => Segs <= "0110001"; WHEN "1101" => Segs <= "1000010"; WHEN "1110" => Segs <= "0110000"; WHEN "1111" => Segs <= "0111000"; WHEN OTHERS => Segs <= "1111111"; END CASE; END PROCESS; END Behavioral; -- 0 -- 1 -- 2 -- 3 -- 4 -- 5 -- 6 -- 7 -- 8 -- 9 -- A -- b -- C -- d -- E -- F -- all off 4

Bin_to_bcd. vhd IF (n >= 90) THEN bcd_tenth <= "1001"; ten : = 90; ELSIF (n >= 80) THEN bcd_tenth <= "1000"; ten : = 80; ELSIF (n >= 70) THEN bcd_tenth <= "0111"; ten : = 70; ELSIF (n >= 60) THEN bcd_tenth <= "0110"; ten : = 60; ELSIF (n >= 50) THEN bcd_tenth <= "0101"; ten : = 50; ELSIF (n >= 40) THEN bcd_tenth <= "0100"; ten : = 40; ELSIF (n >= 30) THEN bcd_tenth <= "0011"; ten : = 30; ELSIF (n >= 20) THEN bcd_tenth <= "0010"; ten : = 20; ELSIF (n >= 10) THEN bcd_tenth <= "0001"; ten : = 10; ELSE bcd_tenth <= "0000"; ten : = 0; END IF; -- this program converts an 8 -bit unsigned value to two BCD values -- if number >= 200, the decimal point for the tenth digit is on -- if 200 > number >= 100, the decimal point for the unit digit is on -- if number < 99, the two decimal digits will be separated into two BCD values LIBRARY IEEE; USE IEEE. std_logic_1164. all; USE ieee. std_logic_unsigned. all; -- for CONV_INTEGER() USE IEEE. std_logic_arith. all; -- for CONV_STD_LOGIC_VECTOR() ENTITY bin_to_bcd IS PORT ( binary: IN STD_LOGIC_VECTOR(7 DOWNTO 0); point 200, point 100: OUT STD_LOGIC; bcd_tenth, bcd_unit: OUT STD_LOGIC_VECTOR(3 DOWNTO 0)); END bin_to_bcd; ARCHITECTURE Behavioral OF bin_to_bcd IS BEGIN PROCESS(binary) VARIABLE n: integer RANGE 0 TO 255; VARIABLE ten: integer RANGE 0 TO 99; VARIABLE unit: integer RANGE 0 TO 9; BEGIN n : = CONV_INTEGER(binary); IF (n >= 200) THEN point 200 <= '1'; n : = n - 100; ELSE point 200 <= '0'; END IF; IF (n >= 100) THEN point 100 <= '1'; n : = n - 100; unit : = n - ten; bcd_unit <= CONV_STD_LOGIC_VECTOR(unit, 4); END Process; ELSE point 100 <= '0'; END IF; END Behavioral; 5

Bin 2 dec. vhd LIBRARY IEEE; USE IEEE. STD_LOGIC_1164. ALL; ENTITY bin 2 dec IS PORT ( input: IN STD_LOGIC_VECTOR(7 DOWNTO 0); Point. N 200, Point. N 100: OUT STD_LOGIC; a. N 10, b. N 10, c. N 10, d. N 10, e. N 10, f. N 10, g. N 10, a. N 1, b. N 1, c. N 1, d. N 1, e. N 1, f. N 1, g. N 1: OUT STD_LOGIC); END bin 2 dec; ARCHITECTURE Structural OF bin 2 dec IS COMPONENT bin_to_bcd PORT ( binary: IN STD_LOGIC_VECTOR(7 DOWNTO 0); point 200, point 100: OUT STD_LOGIC; bcd_tenth, bcd_unit: OUT STD_LOGIC_VECTOR(3 DOWNTO 0)); END COMPONENT; COMPONENT BCD PORT ( in_bcd: IN std_logic_vector(3 DOWNTO 0); segs: OUT std_logic_vector(1 TO 7)); END COMPONENT; BEGIN U 1: bin_to_bcd PORT MAP (input, c_point 200, c_point 100, c_bcd 1); U 2: BCD PORT MAP (c_bcd 10, c_seg 10); U 3: BCD PORT MAP (c_bcd 1, c_seg 1); Point. N 200 <= NOT c_point 200; Point. N 100 <= NOT c_point 100; a. N 10 <= c_seg 10(1); b. N 10 <= c_seg 10(2); c. N 10 <= c_seg 10(3); d. N 10 <= c_seg 10(4); e. N 10 <= c_seg 10(5); f. N 10 <= c_seg 10(6); g. N 10 <= c_seg 10(7); a. N 1 <= c_seg 1(1); b. N 1 <= c_seg 1(2); c. N 1 <= c_seg 1(3); d. N 1 <= c_seg 1(4); e. N 1 <= c_seg 1(5); f. N 1 <= c_seg 1(6); g. N 1 <= c_seg 1(7); END Structural; SIGNAL c_bcd 1, c_bcd 10: STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL c_point 200, c_point 100: STD_LOGIC; SIGNAL c_seg 10, c_seg 1: STD_LOGIC_VECTOR(1 TO 7); 6

BEGIN Mp. vhd LIBRARY IEEE; USE IEEE. STD_LOGIC_1164. ALL; USE IEEE. STD_LOGIC_unsigned. ALL; ENTITY mp IS PORT ( clock, reset : IN STD_LOGIC; input: IN STD_LOGIC_VECTOR(7 DOWNTO 0); enter: IN STD_LOGIC; done: OUT STD_LOGIC; output: OUT STD_LOGIC_VECTOR(7 DOWNTO 0)); END mp; ARCHITECTURE FSMD OF mp IS TYPE state_type IS (s 0, s 1, s 2, s 3); SIGNAL state: state_type; SIGNAL X: STD_LOGIC_VECTOR(7 DOWNTO 0); SIGNAL Largest: STD_LOGIC_VECTOR(7 DOWNTO 0); next_state_logic: PROCESS(reset, clock) BEGIN IF(reset = '1') THEN state <= s 0; Largest <= (OTHERS => '0'); ELSIF(clock'EVENT AND clock = '1') THEN CASE state IS WHEN s 0 => X <= input; IF (enter = '1') THEN state <= s 1; ELSE state <= s 0; END IF; WHEN s 1 => IF (X = "0000") THEN state <= s 3; ELSIF (X > Largest) THEN state <= s 2; ELSIF (enter = '0') THEN state <= s 0; ELSE state <= s 1; END IF; WHEN s 2 => Largest <= X; IF (enter = '0') THEN state <= s 0; ELSE state <= s 2; END IF; WHEN s 3 => state <= s 3; WHEN OTHERS => state <= s 0; END CASE; END IF; END PROCESS; -- all the output signals must be assigned in a process without -- the IF Clock'EVENT condition, otherwise they will be treated -- as storage elements and therefore cannot be tri-stated output_logic: PROCESS(state) BEGIN CASE state IS WHEN s 3 => output <= Largest; done <= '1'; WHEN OTHERS => output <= Largest; done <= '0'; END CASE; END PROCESS; END FSMD; 7

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signal pin number clock Pin_91 Enter Pin_28 Reset Pin_29 a. N 1 Pin_17 a. N 10 Pin_6 input(7) Pin_41 b. N 1 Pin_18 b. N 10 Pin_7 input(6) Pin_40 c. N 1 Pin_19 c. N 10 Pin_8 input(5) Pin_39 d. N 1 Pin_20 d. N 10 Pin_9 input(4) Pin_38 e. N 1 Pin_21 e. N 10 Pin_11 input(3) Pin_36 f. N 1 Pin_23 f. N 10 Pin_12 input(2) Pin_35 g. N 1 Pin_24 g. N 10 Pin_13 input(1) Pin_34 point. N 100 Pin_25 point. N 200 Pin_14 input(0) Pin_33 20

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