1 2 3 4 5 6 Multiplexers Decoders

1. 2. 3. 4. 5. 6. Multiplexers Decoders Encoders Code converters Arithmetic comparison circuits VHDL for combinational circuits

1. Multiplexers s w 0 w 1 0 1 f s f 0 1 w 0 w 1 (b) Truth table (a) Graphical symbol w 0 s f w 1 s w 1 (c) Sum-of-products circuit Figure 6. 1 f (d) Circuit with transmission gates A 2 -to-1 multiplexer

s 0 s 1 w 0 w 1 w 2 w 3 s 1 s 0 00 01 10 11 0 0 1 1 f (a) Graphic symbol 0 1 f w 0 w 1 w 2 w 3 (b) Truth table s 0 w 0 s 1 w 1 f w 2 w 3 (c) Circuit Figure 6. 2 A 4 -to-1 multiplexer

s 1 s 0 w 0 0 w 1 1 0 1 Figure 6. 3 w 2 0 w 3 1 f Using 2 -to-1 multiplexers to build a 4 -to-1 multiplexer

s 0 s 1 w 0 w 3 w 4 s 2 s 3 w 7 f w 8 w 11 w 12 w 15 Figure 6. 4 A 16 -to-1 multiplexer

s x 1 y 1 x 2 y 2 (a) A 2 x 2 crossbar switch x 1 0 1 y 1 s x 2 0 1 y 2 (b) Implementation using multiplexers Figure 6. 5 A practical application of multiplexers

Implementing programmable switches in an FPGA Figure 6. 6

Synthesis of a logic function using multiplexers w 1 w 2 w 1 f 0 0 1 1 1 0 0 1 1 0 f (a) Implementation using a 4 -to-1 multiplexer w 1 w 2 f 0 0 1 1 1 0 (b) Modified truth table Figure 6. 7 w 1 f 0 w 2 1 w 2 w 1 w 2 f (c) Circuit Synthesis of a logic function using multiplexers

w 1 w 2 w 3 0 0 1 1 0 1 0 1 f w 1 w 2 0 0 0 1 1 1 0 0 1 1 0 1 f 0 w 3 1 (a) Modified truth table w 2 w 1 0 w 3 f 1 (b) Circuit Figure 6. 8 Three-input majority function

w 1 w 2 w 3 0 0 1 1 0 1 0 1 f 0 1 1 0 0 1 w 2 Å w 3 w 1 w 3 f w 2 Å w 3 (a) Truth table Figure 6. 9 (b) Circuit Three-input XOR function

w 1 w 2 w 3 0 0 1 1 0 1 0 1 f 0 1 1 0 0 1 w 3 w 2 w 1 w 3 f w 3 (a) Truth table Figure 6. 10 (b) Circuit Three-input XOR function

w 1 w 2 w 3 0 0 1 1 0 1 0 1 f 0 0 0 1 1 1 w 1 f 0 1 w 2 w 3 w 2 + w 3 (b) Truth table w 1 w 2 w 3 f (b) Circuit Figure 6. 11 Three-input majority function using a 2 -to-1 MUX

Boole’s (Shannon’s) Expansion f(w 1, w 2, . . . , wn) = w 1 f(0, w 2, . . . , wn) + w 1 f(1, w 2, . . . , wn) = w 1 fw 1 + w 1 fw 1 = w 1 w 2 f(0, 0, w 3, . . . , wn) + w 1 w 2 f(0, 1, w 3, . . . , wn) + w 1 w 2 f(1, 0, w 3, . . . , wn) + w 1 w 2 f(1, 1, w 3, . . . , wn)

f = w 1 w 2 + w 1 w 3 + w 2 w 3 Shannon’s F=W 1’(W 2 W 3)+W 1(W 2+W 3) F=w 2’(w 1 w 3)+w 2(w 1+w 3)

f = w 1’w 3 + w 2 w 3’ Decomposition using w 1 gives F=W 1’(W 3+W 2 W 3’)+W 1(W 2 W 3’) F=W 1’(W 3+W 2)+W 1(W 2 W 3’) Decomposition using w 2 gives Decomposition using w 3 gives

f = w 1’w 3‘+ w 1 w 2 +w 1 w 3 F=w 1’(w 3’)+w 1(w 2+w 3) F=w 1’w 2’(w 3’)+w 1’w 2(w 3’) +w 1 w 2’(w 3)+w 1 w 2(1) Figure 6. 12 Example circuits

f = w 1 w 2 + w 1 w 3 + w 2 w 3 w 2 w 1 g=w 2’(0)+w 2(w 3) h=w 2’(w 3)+w 2(1) 0 w 3 f 1 Figure 6. 13 Example circuit

f = w 2’w 3+w 1’w 2 w 3’+ w 2 w 3’w 4+w 1 w 2’w 4’ F=w 1’fw 1’+w 1 fw 1 =w 1’(w 2’w 3+w 2 w 3’w 4) +w 1(w 2’w 3+w 2 w 3’w 4+w 2’w 4’) F=w 2’fw 2’+w 2 fw 2 =w 2’(w 3+w 1 w 4’)+w 2(w 1’w 3’+w 3’w 4)

w 1 0 w 2 w 3 fw 1 f fw 1 w 4 (a) Using three 3 -LUTs w 2 0 w 1 w 3 w 4 fw 2 (b) Using two 3 -LUTs Figure 6. 14 Example circuits f

2. DECODERS w 0 n inputs Enable Figure 6. 15 y 0 2 n outputs wn – 1 En y 2 n – 1 An n-to-2 n decoder

En w 1 w 0 1 1 0 0 0 1 1 x 0 1 x y 0 y 1 y 2 y 3 1 0 0 0 0 0 1 0 (a) Truth table w 0 w 1 En y 0 y 1 y 2 y 3 (b) Graphic symbol w 0 y 0 w 1 y 2 y 3 En (c) Logic circuit Figure 6. 16 A 2 -to-4 decoder

w 0 w 1 w 2 En w 0 w 1 En Figure 6. 17 y 0 y 1 y 2 y 3 y 4 y 5 y 6 y 7 A 3 -to-8 decoder using two 2 -to-4 decoder

w 0 w 1 En w 0 w 1 w 2 w 3 w 0 w 1 En En y 0 y 1 y 2 y 3 En w 0 w 1 En Figure 6. 18 y 0 y 1 y 2 y 3 y 4 y 5 y 6 y 7 y 0 y 1 y 2 y 3 y 8 y 9 y 10 y 11 y 0 y 1 y 2 y 3 y 12 y 13 y 14 y 15 A 4 -to-16 decoder built using a decoder tree

w 0 w 1 s 0 s 1 1 w 0 w 1 En y 0 y 1 y 2 y 3 f w 2 w 3 Figure 6. 19 A 4 -to-1 multiplexer built using a decoder

w 0 s 1 1 w 0 w 1 En y 0 y 1 y 2 y 3 w 1 f w 2 w 3 Figure 6. 20 A 4 -to-1 multiplexer built using a decoder and tri-state buffers

Demultiplexers • A demultiplexer is a circuit which places the value of a single data input onto multiple data outputs is a demultiplexer. w 0 y 0 w 1 y 2 y 3 En

Sel 0 a 0 Address a 1 am – 1 m-to-2 m decoder Sel 1 Sel 2 m – 1 0/1 0/1 0/1 Read Data Figure 6. 21 dn – 2 A 2 m x n read-only memory (ROM) block d 0

3. ENCODERS w 0 2 n inputs w 2 n – 1 Figure 6. 22 y 0 yn – 1 n outputs A 2 n-to-n binary encoder

BINARY ENCODER w 3 w 2 w 1 w 0 0 1 0 0 0 y 1 y 0 0 0 1 1 0 1 (a) Truth table w 0 w 1 y 0 w 2 y 1 w 3 (b) Circuit Figure 6. 23 A 4 -to-2 binary encoder

PRIORITY ENCODER w 3 w 2 w 1 w 0 0 0 1 x x 0 1 x x x y 1 y 0 z d 0 0 1 1 1 1 d 0 1 Figure 6. 24. Truth table for a 4 -to-2 priority encoder.

4 CODE CONVERTERS a w 0 w 1 w 2 w 3 a b c d e f g f e w 3 w 2 w 1 w 0 (a) Code converter 0 0 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 a b c d e f g 1 0 1 1 1 0 0 1 1 1 1 0 1 1 0 1 0 0 0 1 1 1 0 0 1 1 1 0 1 1 b g c d (b) 7 -segment display (c) Truth table Figure 6. 25. A BCD-to-7 -segment display code converter.

5 ARITHMETIC COMPARISIONS Figure 6. 26. A four-bit comparator circuit.

Libraries • Library ieee; • • Use ieee. std_logic_1164. all; Use ieee. std_logic_arith. all; Use ieee. std_logic_signed. all; Use ieee. std_logic_unsigned. all;

Data Types • bit values: '0', '1' • boolean values: TRUE, FALSE • integer values: -(231) to +(231 - 1) • std_logic values: 'U', 'X', '1', '0', 'Z', 'W', 'H', 'L', '-' U' = uninitialized 'X' = unknown 'W' = weak 'X‘ 'Z' = floating 'H'/'L' = weak '1'/'0‘ '-' = don't care

Entity • Define inputs and outputs • Example: Entity test is Port( A, B, C, D: in std_logic; E: out std_logic); End test;

Architecture • Define functionality of the chip • X <= A AND B; • Y <= C AND D; • E <= X OR Y;

VHDL features • Case insensitive – inputa, INPUTA and Input. A are refer to same variable • Comments – ‘--’ until end of line – If you want to comment multiple lines, ‘--’ need to be put at the beginning of every single line • Statements are terminated by ‘; ’ • Signal assignment: – ‘<=’ • User defined names: – letters, numbers, underscores (‘_’) – start with a letter

VHDL structure • Library – Definitions, constants • Entity – Interface • Architecture – Implementation, function

VHDL - Library • Include library IEEE; – Define the library package used use IEEE. STD_LOGIC_1164. all; – Define the library file used – For example, STD_LOGIC_1164 defines ‘ 1’ as logic high and ‘ 0’ as logic low • output <= ‘ 1’; --Assign logic high to output

Reserved VHDL keywords ABS ACCESS AFTER ALIAS ALL AND ARCHITECTURE ARRAY ASSERT ATTRIBUTE BEGIN BLOCK BODY BUFFER BUS CASE COMPONENT CONFIGURATION CONSTANT DISCONNECT DOWNTO ELSE ELSIF END ENTITY EXIT FILE FOR FUNCTION GENERATE GENERIC GROUP GUARDED IF IMPURE IN INERTIAL INOUT IS LABEL LIBRARY LINKAGE LITERAL LOOP MAP MOD NAND NEW NEXT NOR NOT NULL OF ON OPEN OR OTHERS OUT PACKAGE PORT POSTPONED PROCEDURE PROCESS PURE RANGE RECORD REGISTER REM REPORT ROL ROR RETURN VARIABLE SELECT SEVERITY SIGNAL SHARED SLA SLL SRA SRL SUBTYPE WAIT WHEN WHILE WITH THEN TO TRANSPORT TYPE UNAFFECTED UNITS UNTIL USE XNOR XOR

Entity Declaration • Entity Declaration describes the interface of the component, i. e. input and output ports. Entity name Port names Port type ENTITY nand_gate IS PORT( a : IN STD_LOGIC; b : IN STD_LOGIC; z : OUT STD_LOGIC ); END nand_gate; Reserved words Port modes (data flow directions) Semicolon No Semicolon

Entity declaration – simplified syntax ENTITY entity_name IS PORT ( port_name : signal_mode signal_type; …………. port_name : signal_mode signal_type); END entity_name;

Architecture • Describes an implementation of a design entity. • Architecture example: ARCHITECTURE model OF nand_gate IS BEGIN z <= a NAND b; END model;

Architecture – simplified syntax ARCHITECTURE architecture_name OF entity_name IS [ declarations ] BEGIN code END architecture_name;

Entity Declaration & Architecture nand_gate. vhd LIBRARY ieee; USE ieee. std_logic_1164. all; ENTITY nand_gate IS PORT( a : IN STD_LOGIC; b : IN STD_LOGIC; z : OUT STD_LOGIC); END nand_gate; ARCHITECTURE model OF nand_gate IS BEGIN z <= a NAND b; END model;

Port Modes The Port Mode of the interface describes the direction in which data travels with respect to the component – In: Data comes in this port and can only be read within the entity. It can appear only on the right side of a signal or variable assignment. – Out: The value of an output port can only be updated within the entity. It cannot be read. It can only appear on the left side of a signal assignment. – Inout: The value of a bi-directional port can be read and updated within the entity model. It can appear on both sides of a signal assignment. – Buffer: Used for a signal that is an output from an entity. The value of the signal can be used inside the entity, which means that in an assignment statement the signal can appear on the left and right sides of the <= operator

Library declarations Library declaration LIBRARY ieee; USE ieee. std_logic_1164. all; Use all definitions from the package std_logic_1164 ENTITY nand_gate IS PORT( a : IN STD_LOGIC; b : IN STD_LOGIC; z : OUT STD_LOGIC); END nand_gate; ARCHITECTURE model OF nand_gate IS BEGIN z <= a NAND b; END model;

Library declarations - syntax LIBRARY library_name; USE library_name. package_parts;

Fundamental parts of a library LIBRARY PACKAGE 1 TYPES CONSTANTS FUNCTIONS PROCEDURES COMPONENTS PACKAGE 2 TYPES CONSTANTS FUNCTIONS PROCEDURES COMPONENTS

• ieee Libraries Specifies multi-level logic system, including STD_LOGIC, and STD_LOGIC_VECTOR data types Need to be explicitly declared • std Specifies pre-defined data types (BIT, BOOLEAN, INTEGER, REAL, SIGNED, UNSIGNED, etc. ), arithmetic operations, basic type conversion functions, basic text i/o functions, etc. • work Current designs after compilation Visible by default

Operations on Unsigned Numbers For operations on unsigned numbers USE ieee. std_logic_unsigned. all and signals (inputs/outputs) of the type STD_LOGIC_VECTOR OR USE ieee. std_logic_arith. all and signals (inputs/outputs) of the type UNSIGNED

Operations on Signed Numbers For operations on signed numbers USE ieee. std_logic_signed. all and signals (inputs/outputs) of the type STD_LOGIC_VECTOR OR USE ieee. std_logic_arith. all and signals (inputs/outputs) of the type SIGNED

Signed and Unsigned Types Behave exactly like STD_LOGIC_VECTOR plus, they determine whether a given vector should be treated as a signed or unsigned number. Require USE ieee. std_logic_arith. all;

Integer Types Operations on signals (variables) of the integer types: INTEGER, NATURAL, and their sybtypes, such as TYPE day_of_month IS RANGE 0 TO 31; are synthesizable in the range -(231 -1). . 231 -1 for INTEGERs and their subtypes 0. . 231 -1 for NATURALs and their subtypes

Integer Types Operations on signals (variables) of the integer types: INTEGER, NATURAL, are less flexible and more difficult to control than operations on signals (variables) of the type STD_LOGIC_VECTOR UNSIGNED, and thus are recommened to be avoided by beginners.

6. VHDL FOR COMBINATIONAL CIRCUITS 6. 1 Assignment statements selected signal assignment conditional signal assignment generate statements if-then-else statements case statements

SELECTED SIGNAL ASSIGNMENT LIBRARY ieee ; USE ieee. std_logic_1164. all ; ENTITY mux 2 to 1 IS PORT ( w 0, w 1, s f END mux 2 to 1 ; : IN : OUT STD_LOGIC ; STD_LOGIC ) ; ARCHITECTURE Behavior OF mux 2 to 1 IS BEGIN WITH s SELECT f <= w 0 WHEN '0', w 1 WHEN OTHERS ; END Behavior ; Figure 6. 27 VHDL code for a 2 -to-1 multiplexer

LIBRARY ieee ; USE ieee. std_logic_1164. all ; ENTITY mux 4 to 1 IS PORT ( w 0, w 1, w 2, w 3 s f END mux 4 to 1 ; : IN : OUT STD_LOGIC ; STD_LOGIC_VECTOR(1 DOWNTO 0) ; STD_LOGIC ) ; ARCHITECTURE Behavior OF mux 4 to 1 IS BEGIN WITH s SELECT f <= w 0 WHEN "00", w 1 WHEN "01", w 2 WHEN "10", w 3 WHEN OTHERS ; END Behavior ; Figure 6. 28 VHDL code for a 4 -to-1 multiplexer

LIBRARY ieee ; USE ieee. std_logic_1164. all ; PACKAGE mux 4 to 1_package IS COMPONENT mux 4 to 1 PORT ( w 0, w 1, w 2, w 3 : IN STD_LOGIC ; s : IN STD_LOGIC_VECTOR(1 DOWNTO 0) ; f : OUT STD_LOGIC ) ; END COMPONENT ; END mux 4 to 1_package ; Figure 6. 28 Component declaration for the 4 -to-1 multiplexer

LIBRARY ieee ; USE ieee. std_logic_1164. all ; LIBRARY work ; USE work. mux 4 to 1_package. all ; ENTITY mux 16 to 1 IS PORT ( w : IN s : IN f : OUT END mux 16 to 1 ; STD_LOGIC_VECTOR(0 TO 15) ; STD_LOGIC_VECTOR(3 DOWNTO 0) ; STD_LOGIC ) ; ARCHITECTURE Structure OF mux 16 to 1 IS SIGNAL m : STD_LOGIC_VECTOR(0 TO 3) ; BEGIN Mux 1: mux 4 to 1 PORT MAP ( w(0), w(1), w(2), w(3), s(1 DOWNTO 0), m(0) ) ; Mux 2: mux 4 to 1 PORT MAP ( w(4), w(5), w(6), w(7), s(1 DOWNTO 0), m(1) ) ; Mux 3: mux 4 to 1 PORT MAP ( w(8), w(9), w(10), w(11), s(1 DOWNTO 0), m(2) ) ; Mux 4: mux 4 to 1 PORT MAP ( w(12), w(13), w(14), w(15), s(1 DOWNTO 0), m(3) ) ; Mux 5: mux 4 to 1 PORT MAP ( m(0), m(1), m(2), m(3), s(3 DOWNTO 2), f ) ; END Structure ; Figure 6. 29 Hierarchical code for a 16 -to-1 multiplexer

LIBRARY ieee ; USE ieee. std_logic_1164. all ; ENTITY dec 2 to 4 IS PORT ( w : IN En : IN y : OUT END dec 2 to 4 ; STD_LOGIC_VECTOR(1 DOWNTO 0) ; STD_LOGIC_VECTOR(0 TO 3) ) ; ARCHITECTURE Behavior OF dec 2 to 4 IS SIGNAL Enw : STD_LOGIC_VECTOR(2 DOWNTO 0) ; BEGIN Enw <= En & w ; WITH Enw SELECT y <= "1000" WHEN "100", "0100" WHEN "101", "0010" WHEN "110", "0001" WHEN "111", "0000" WHEN OTHERS ; END Behavior ; Figure 6. 30 VHDL code for a 2 -to-4 binary decoder

CONDITIONAL SIGNAL ASSIGNMENT LIBRARY ieee ; USE ieee. std_logic_1164. all ; ENTITY mux 2 to 1 IS PORT ( w 0, w 1, s f END mux 2 to 1 ; : IN : OUT STD_LOGIC ; STD_LOGIC ) ; ARCHITECTURE Behavior OF mux 2 to 1 IS BEGIN f <= w 0 WHEN s = '0' ELSE w 1 ; END Behavior ; Figure 6. 31 A 2 -to-1 multiplexer using a conditional signal assignment

LIBRARY ieee ; USE ieee. std_logic_1164. all ; ENTITY priority IS PORT ( w : IN y : OUT z : OUT END priority ; STD_LOGIC_VECTOR(3 DOWNTO 0) ; STD_LOGIC_VECTOR(1 DOWNTO 0) ; STD_LOGIC ) ; ARCHITECTURE Behavior OF priority IS BEGIN y <= "11" WHEN w(3) = '1' ELSE "10" WHEN w(2) = '1' ELSE "01" WHEN w(1) = '1' ELSE "00" ; z <= '0' WHEN w = "0000" ELSE '1' ; END Behavior ; Figure 6. 32 VHDL code for a priority encoder

LIBRARY ieee ; USE ieee. std_logic_1164. all ; ENTITY priority IS PORT ( w : IN y : OUT z : OUT END priority ; STD_LOGIC_VECTOR(3 DOWNTO 0) ; STD_LOGIC_VECTOR(1 DOWNTO 0) ; STD_LOGIC ) ; ARCHITECTURE Behavior OF priority IS BEGIN WITH w SELECT y <= "00" WHEN "0001", "01" WHEN "0010", "01" WHEN "0011", "10" WHEN "0100", "10" WHEN "0101", "10" WHEN "0110", "10" WHEN "0111", "11" WHEN OTHERS ; WITH w SELECT z <= '0' WHEN "0000", '1' WHEN OTHERS ; END Behavior ; Figure 6. 33 Less efficient code for a priority encoder

LIBRARY ieee ; USE ieee. std_logic_1164. all ; USE ieee. std_logic_unsigned. all ; ENTITY compare IS PORT ( A, B : IN Aeq. B, Agt. B, Alt. B : OUT END compare ; STD_LOGIC_VECTOR(3 DOWNTO 0) ; STD_LOGIC ) ; ARCHITECTURE Behavior OF compare IS BEGIN Aeq. B <= '1' WHEN A = B ELSE '0' ; Agt. B <= '1' WHEN A > B ELSE '0' ; Alt. B <= '1' WHEN A < B ELSE '0' ; END Behavior ; Figure 6. 34 VHDL code for a four-bit comparator

LIBRARY ieee ; USE ieee. std_logic_1164. all ; USE ieee. std_logic_arith. all ; ENTITY compare IS PORT ( A, B : IN Aeq. B, Agt. B, Alt. B : OUT END compare ; SIGNED(3 DOWNTO 0) ; STD_LOGIC ) ; ARCHITECTURE Behavior OF compare IS BEGIN Aeq. B <= '1' WHEN A = B ELSE '0' ; Agt. B <= '1' WHEN A > B ELSE '0' ; Alt. B <= '1' WHEN A < B ELSE '0' ; END Behavior ; Figure 6. 35 A four-bit comparator using signed numbers

GENERATE STATEMENTS LIBRARY ieee ; USE ieee. std_logic_1164. all ; USE work. mux 4 to 1_package. all ; ENTITY mux 16 to 1 IS PORT ( w : IN s : IN f : OUT END mux 16 to 1 ; STD_LOGIC_VECTOR(0 TO 15) ; STD_LOGIC_VECTOR(3 DOWNTO 0) ; STD_LOGIC ) ; ARCHITECTURE Structure OF mux 16 to 1 IS SIGNAL m : STD_LOGIC_VECTOR(0 TO 3) ; BEGIN G 1: FOR i IN 0 TO 3 GENERATE Muxes: mux 4 to 1 PORT MAP ( w(4*i), w(4*i+1), w(4*i+2), w(4*i+3), s(1 DOWNTO 0), m(i) ) ; END GENERATE ; Mux 5: mux 4 to 1 PORT MAP ( m(0), m(1), m(2), m(3), s(3 DOWNTO 2), f ) ; END Structure ; Figure 6. 36 Code for a 16 -to-1 multiplexer using a generate statement

LIBRARY ieee ; USE ieee. std_logic_1164. all ; ENTITY dec 4 to 16 IS PORT ( w : IN En : IN y : OUT END dec 4 to 16 ; STD_LOGIC_VECTOR(3 DOWNTO 0) ; STD_LOGIC_VECTOR(0 TO 15) ) ; ARCHITECTURE Structure OF dec 4 to 16 IS COMPONENT dec 2 to 4 PORT ( w : IN STD_LOGIC_VECTOR(1 DOWNTO 0) ; En : IN STD_LOGIC ; y : OUT STD_LOGIC_VECTOR(0 TO 3) ) ; END COMPONENT ; SIGNAL m : STD_LOGIC_VECTOR(0 TO 3) ; BEGIN G 1: FOR i IN 0 TO 3 GENERATE Dec_ri: dec 2 to 4 PORT MAP ( w(1 DOWNTO 0), m(i), y(4*i TO 4*i+3) ); G 2: IF i=3 GENERATE Dec_left: dec 2 to 4 PORT MAP ( w(i DOWNTO i-1), En, m ) ; END GENERATE ; END Structure ; Figure 6. 37 Hierarchical code for a 4 -to-16 binary decoder

Concurrent vs. Sequential • All previous statements are called concurrent assignment statements because order does not matter. • When order matters, the statements are called sequential assignment statements. • All sequential assignment statements are placed within a process statement.

Process Statement • Begins with PROCESS keyword followed by a sensitivity list. • For a combinational circuit, sensitivity list includes all input signals used in the process. • Process executed whenever there is a change on a signal in the sensitivity list. • Statements executed in sequential order. • No assignments are visible until all statements in the process have been executed. • If multiple assignments, only last has an effect.

LIBRARY ieee ; USE ieee. std_logic_1164. all ; ENTITY mux 2 to 1 IS PORT ( w 0, w 1, s f END mux 2 to 1 ; : IN : OUT STD_LOGIC ; STD_LOGIC ) ; ARCHITECTURE Behavior OF mux 2 to 1 IS BEGIN PROCESS ( w 0, w 1, s ) BEGIN IF s = '0' THEN f <= w 0 ; ELSE f <= w 1 ; END IF ; END PROCESS ; END Behavior ; Figure 6. 38 A 2 -to-1 multiplexer specified using an if-then-else statement

LIBRARY ieee ; USE ieee. std_logic_1164. all ; ENTITY mux 2 to 1 IS PORT ( w 0, w 1, s f END mux 2 to 1 ; : IN : OUT STD_LOGIC ; STD_LOGIC ) ; ARCHITECTURE Behavior OF mux 2 to 1 IS BEGIN PROCESS ( w 0, w 1, s ) BEGIN f <= w 0 ; IF s = '1' THEN f <= w 1 ; END IF ; END PROCESS ; END Behavior ; Figure 6. 39 Alternative code for a 2 -to-1 multiplexer

LIBRARY ieee ; USE ieee. std_logic_1164. all ; ENTITY priority IS PORT ( w : IN y : OUT z : OUT END priority ; STD_LOGIC_VECTOR(3 DOWNTO 0) ; STD_LOGIC_VECTOR(1 DOWNTO 0) ; STD_LOGIC ) ; ARCHITECTURE Behavior OF priority IS BEGIN PROCESS ( w ) BEGIN IF w(3) = '1' THEN y <= "11" ; ELSIF w(2) = '1' THEN y <= "10" ; ELSIF w(1) = '1' THEN y <= "01" ; ELSE y <= "00" ; END IF ; END PROCESS ; z <= '0' WHEN w = "0000" ELSE '1' ; END Behavior ; Figure 6. 40 A priority encoder specified using if-then-else

LIBRARY ieee ; USE ieee. std_logic_1164. all ; ENTITY priority IS PORT ( w y z END priority ; : IN : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) ; STD_LOGIC_VECTOR(1 DOWNTO 0) ; STD_LOGIC ) ; ARCHITECTURE Behavior OF priority IS BEGIN PROCESS ( w ) BEGIN y <= "00" ; IF w(1) = '1' THEN y <= "01" ; END IF ; IF w(2) = '1' THEN y <= "10" ; END IF ; IF w(3) = '1' THEN y <= "11" ; END IF ; z <= '1' ; IF w = "0000" THEN z <= '0' ; END IF ; END PROCESS ; END Behavior ; Figure 6. 41 Alternative code for the priority encoder

LIBRARY ieee ; USE ieee. std_logic_1164. all ; ENTITY compare 1 IS PORT ( A, B Aeq. B END compare 1 ; : IN : OUT STD_LOGIC ; STD_LOGIC ) ; ARCHITECTURE Behavior OF compare 1 IS BEGIN PROCESS ( A, B ) BEGIN Aeq. B <= '0' ; IF A = B THEN Aeq. B <= '1' ; END IF ; END PROCESS ; END Behavior ; Figure 6. 42 Code for a one-bit equality comparator

LIBRARY ieee ; USE ieee. std_logic_1164. all ; ENTITY implied IS PORT ( A, B Aeq. B END implied ; : IN : OUT STD_LOGIC ; STD_LOGIC ) ; ARCHITECTURE Behavior OF implied IS BEGIN PROCESS ( A, B ) BEGIN IF A = B THEN Aeq. B <= '1' ; END IF ; END PROCESS ; END Behavior ; Figure 6. 43 An example of code that results in implied memory

… PROCESS ( A, B ) BEGIN IF A = B THEN Aeq. B <= '1' ; END IF ; END PROCESS ; … A B Figure 6. 44 Aeq. B Circuit generated due to implied memory

CASE STATEMENTS LIBRARY ieee ; USE ieee. std_logic_1164. all ; ENTITY mux 2 to 1 IS PORT ( w 0, w 1, s f END mux 2 to 1 ; : IN STD_LOGIC ; : OUT STD_LOGIC ) ; ARCHITECTURE Behavior OF mux 2 to 1 IS BEGIN PROCESS ( w 0, w 1, s ) BEGIN CASE s IS WHEN '0' => f <= w 0 ; WHEN OTHERS => f <= w 1 ; END CASE ; END PROCESS ; END Behavior ; Figure 6. 45 A CASE statement that represents a 2 -to-1 multiplexer

LIBRARY ieee ; USE ieee. std_logic_1164. all ; ENTITY dec 2 to 4 IS PORT ( w : IN En : IN y : OUT END dec 2 to 4 ; STD_LOGIC_VECTOR(1 DOWNTO 0) ; STD_LOGIC_VECTOR(0 TO 3) ) ; ARCHITECTURE Behavior OF dec 2 to 4 IS BEGIN PROCESS ( w, En ) BEGIN IF En = '1' THEN CASE w IS WHEN "00" => WHEN "01" => WHEN "10" => WHEN OTHERS => END CASE ; ELSE y <= "0000" ; END IF ; END PROCESS ; END Behavior ; Figure 6. 46 y <= "1000" ; y <= "0100" ; y <= "0010" ; y <= "0001" ; A 2 -to-4 binary decoder

LIBRARY ieee ; USE ieee. std_logic_1164. all ; ENTITY seg 7 IS PORT ( bcd : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ; leds : OUT STD_LOGIC_VECTOR(1 TO 7) ) ; END seg 7 ; ARCHITECTURE Behavior OF seg 7 IS BEGIN PROCESS ( bcd ) BEGIN CASE bcd IS -abcdefg WHEN "0000" => leds <= "1111110" ; WHEN "0001" => leds <= "0110000" ; WHEN "0010" => leds <= "1101101" ; WHEN "0011" => leds <= "1111001" ; WHEN "0100" => leds <= "0110011" ; WHEN "0101" => leds <= "1011011" ; WHEN "0110" => leds <= "1011111" ; WHEN "0111" => leds <= "1110000" ; WHEN "1000" => leds <= "1111111" ; WHEN "1001" => leds <= "1110011" ; WHEN OTHERS => leds <= "-------" ; END CASE ; END PROCESS ; END Behavior ; Figure 6. 47 A BCD-to-7 -segment decoder

Table 6. 1 The functionality of the 74381 ALU

LIBRARY ieee ; USE ieee. std_logic_1164. all ; USE ieee. std_logic_unsigned. all ; ENTITY alu IS PORT ( s : IN STD_LOGIC_VECTOR(2 DOWNTO 0) ; A, B : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ; F : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) ) ; END alu ; ARCHITECTURE Behavior OF alu IS BEGIN PROCESS ( s, A, B ) BEGIN CASE s IS WHEN "000" => F <= "0000" ; WHEN "001" => F <= B - A ; WHEN "010" => F <= A - B ; Figure 6. 48 Code that WHEN "011" => F <= A + B ; represents the functionality WHEN "100" => F <= A XOR B ; of the 74381 ALU WHEN "101" => F <= A OR B ; WHEN "110" => F <= A AND B ; WHEN OTHERS => F <= "1111" ; END CASE ; END PROCESS ; END Behavior ;

Figure 6. 49 Timing simulation for the 74381 ALU code