01 2 fulladder FA v carry Cin X

  • Slides: 83
Download presentation

01 가산기 2. 전가산기(full-adder, FA) v 자리 올림수(carry)를 고려하여 만든 덧셈 회로 Cin X

01 가산기 2. 전가산기(full-adder, FA) v 자리 올림수(carry)를 고려하여 만든 덧셈 회로 Cin X + Y Cout S 0 0 + 0 0 0 1 0 + 0 0 1 입력 0 1 + 0 0 1 1 1 + 0 1 0 출력 X Y Cin S Cout 0 0 1 1 0 1 0 1 0 1 1 0 0 0 1 1 1 - 5 - 0 0 + 1 0 1 1 0 + 1 1 0 0 1 + 1 1 0 1 1 + 1 1 1

01 가산기 BCD 덧셈표 K 0 0 0 0 1 1 Z 8 0

01 가산기 BCD 덧셈표 K 0 0 0 0 1 1 Z 8 0 0 0 0 1 1 1 1 0 0 2진 합 Z 4 0 0 0 0 1 1 1 1 0 0 Z 2 0 0 1 1 0 0 1 1 Z 1 0 1 0 1 0 1 C 0 0 0 0 0 1 1 1 1 1 - 14 - S 8 0 0 0 0 1 1 BCD 합 S 4 S 2 0 0 0 0 0 1 0 1 1 1 1 0 0 0 0 S 1 0 1 0 1 0 1 10진 값 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

02 비교기 q 2비트 비교기 입력 출력 X≠Y X>Y X Y X=Y X 1

02 비교기 q 2비트 비교기 입력 출력 X≠Y X>Y X Y X=Y X 1 X 2 Y 1 Y 2 F 1 F 2 F 3 F 4 00 01 10 11 1 0 0 0 0 1 0 1 1 1 1 0 0 0 1 0 0 0 1 1 1 0 0 0 1 0 0 00 01 10 11 - 17 - X<Y

02 비교기 입력 A 3, B 3 A 2, B 2 A 1, B

02 비교기 입력 A 3, B 3 A 2, B 2 A 1, B 1 A 0, B 0 A 3>B 3 A 3<B 3 A 3=B 3 A 3=B 3 A 3=B 3 A 3=B 3 X X A 2>B 2 A 2<B 2 A 2=B 2 A 2=B 2 A 2=B 2 X X A 1>B 1 A 1<B 1 A 1=B 1 A 1=B 1 A 1=B 1 X X X A 0>B 0 A 0<B 0 A 0=B 0 A 0=B 0 출력 AGBO ALBO AEBO AGBI ALBI AEBI A>B A<B A=B X X X 1 0 0 X X X 0 1 0 1 0 0 0 1 0 0 1 1 0 0 1 1 1 0 0 0 0 1 1 0 4비트 비교기 IC 7485 진리표 - 21 -

03 디코더 4. 4× 16 디코더 D C B A 0 0 0 0

03 디코더 4. 4× 16 디코더 D C B A 0 0 0 0 1 1 1 1 0 0 1 1 0 1 0 1 Y 15 Y 14 Y 13 Y 12 Y 11 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 Y 10 Y 9 Y 8 Y 7 Y 6 Y 5 Y 4 Y 3 Y 2 Y 1 Y 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 4× 16 디코더 진리표 - 34 -

03 디코더 4. 4× 16 디코더 D C B A 0 0 0 0

03 디코더 4. 4× 16 디코더 D C B A 0 0 0 0 1 1 1 1 0 0 1 1 0 1 0 1 Y 15 Y 14 Y 13 Y 12 Y 11 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 Y 10 Y 9 Y 8 Y 7 Y 6 Y 5 Y 4 Y 3 Y 2 Y 1 Y 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 4× 16 디코더 진리표 - 37 -

03 디코더 7 -세그먼트 디코더 진리표 입력 출력 D C B A 0 0

03 디코더 7 -세그먼트 디코더 진리표 입력 출력 D C B A 0 0 0 0 1 1 1 1 0 0 1 1 0 1 0 1 0 1 0 0 0 x x x 0 0 0 1 1 0 0 0 x x x - 43 - 0 0 1 0 0 0 0 x x x 0 1 0 0 1 x x x 0 1 1 1 0 0 0 1 0 0 x x x 1 1 0 0 0 1 0 0 x x x

03 디코더 7447 진리표 0 1 2 decimal or function 0 1 2 3

03 디코더 7447 진리표 0 1 2 decimal or function 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 　 1 1 1 1 X 　 　 3 4 입력 출력 1 X X X X D 0 0 0 0 1 1 1 1 X C 0 0 0 0 1 1 1 1 X B 0 0 1 1 X A 0 1 0 1 X 1 1 1 1 0 0 1 0 1 0 0 0 1 1 0 0 0 1 1 1 1 0 0 0 0 0 1 1 1 0 1 0 0 1 1 0 1 0 1 1 0 1 1 1 0 0 0 1 1 0 0 0 0 1 1 1 0 0 0 1 1 1 1 0 X X X 1 0 0 0 0 5 6 7 8 - 47 - 9 10 11 12 13 14 15

04 인코더 6. 10진-BCD 우선순위 인코더 입력 출력 I 9 I 8 I 7

04 인코더 6. 10진-BCD 우선순위 인코더 입력 출력 I 9 I 8 I 7 I 6 I 5 I 4 I 3 I 2 I 1 1 1 1 1 0 X 1 1 0 1 1 1 1 0 X X 1 1 0 0 1 1 1 0 X X X 1 0 1 1 1 0 X X X 1 0 0 1 1 1 0 X X X 1 0 0 0 1 0 X X X X 0 1 1 1 1 1 진리표 - 60 -

Kippis Skl Cheers Jamas Serefe Cin cin MaailmassaKippis Skl Cheers Jamas Serefe Cin cin Maailmassa
3 1 1 cin include iostream n cin3 1 1 cin include iostream n cin
CIN MRGEZS GYGYSZERREL AZ EGSZSGRT ALAPTVNY BUDAPEST CINCIN MRGEZS GYGYSZERREL AZ EGSZSGRT ALAPTVNY BUDAPEST CIN
CIN 2 ve CIN 3lerde LEEPin Yeri DrCIN 2 ve CIN 3lerde LEEPin Yeri Dr
PORT CARRY DEPORT DE AWAY PORT CARRY ToPORT CARRY DEPORT DE AWAY PORT CARRY To
Support Carry Viewgraph 2 Firemans Carry Viewgraph 3Support Carry Viewgraph 2 Firemans Carry Viewgraph 3
Backpac k Carry Backpack Cases Carry Cases RetailBackpac k Carry Backpack Cases Carry Cases Retail
Backpac k Carry Backpack Cases Carry Cases RetailBackpac k Carry Backpack Cases Carry Cases Retail
5 Carry Trade pg 74 1 The carry5 Carry Trade pg 74 1 The carry
Adders FullAdder The Binary Adder Express Sum andAdders FullAdder The Binary Adder Express Sum and
each of these is an instantiation of fulladdereach of these is an instantiation of fulladder
7 Ch Prof Seewhy Lee Presents 2 fulladder7 Ch Prof Seewhy Lee Presents 2 fulladder
The Compatibility 6 FullAdder Topologies with VDD StackingThe Compatibility 6 FullAdder Topologies with VDD Stacking
Figure 5 2 Halfadder Figure 5 4 FulladderFigure 5 2 Halfadder Figure 5 4 Fulladder
CarryRipple Adder Using fulladder instead of halfadder forCarryRipple Adder Using fulladder instead of halfadder for
Verilog Onebit Full Adder module fulladder A BVerilog Onebit Full Adder module fulladder A B
Aula Nmero 03 Estrutura Sequencial COUT CIN COUTAula Nmero 03 Estrutura Sequencial COUT CIN COUT
1 Problema Auxlio Compras na Web CIn UFPE1 Problema Auxlio Compras na Web CIn UFPE
VIII Encontro CIn sobre Qualidade Processos e GestoVIII Encontro CIn sobre Qualidade Processos e Gesto
Redes Neurais Autoorganizveis Teresa B Ludermir Cin UFPERedes Neurais Autoorganizveis Teresa B Ludermir Cin UFPE
Universidad Nacional de Trujillo A CEN TUA CINUniversidad Nacional de Trujillo A CEN TUA CIN
Management of Women with CIN 1 or LSILManagement of Women with CIN 1 or LSIL
Ontologias Prof Fred Freitas CIn UFPE Prof FredOntologias Prof Fred Freitas CIn UFPE Prof Fred
CIN 23 and AIS Established Surrogate Markers forCIN 23 and AIS Established Surrogate Markers for